Sponsors by:
IEEE Macau Section CAS/COM Joint Chapter

Support by:
University of Macau
Mentor Graphics
IEEE Macau Section

Keynote Addresses

Opening & Keynote I : Jan. 26, 2016 (9:00-10:00am)

Chairman: Rui P. Martins, University of Macau, Macao, China

The Next Decade

Alessandro Cremonesi

Alessandro Cremonesi

Group Vice President, General Manager of ST Central Labs at STMicroelectronics

In his speech Alessandro Cremonesi will give his perspective of major trends in electronics for the next decade. New services and applications will be fueled by the evolution of the electronic systems and by the evolution of the cloud technologies. Both together will bring us to a new way to handle our life, our work, our social interactions and our interaction with the environment. We will have lot of challenges in front of us but also new tools and methods to handle them.

Alessandro Cremonesi is Group Vice President, General Manager of ST Central Labs at STMicroelectronics. In this role, he manages the Company’s Labs dedicated to System Application and Innovation worldwide with responsibilities that span from corporate advanced R&D to system-solutions support for ST customers. Cremonesi performs institutional and advisory roles with several industrial and academic bodies. He has authored several technical papers and patents in analog and digital signal processing and is a member of the Scientific Advisory Board at IMEC.

Keynote II : Jan. 27, 2016 (9:00-10:00am)

Chairman: Pui-In Mak (University of Macau, Macao)

Systems of Systems - The Next Frontier of Semiconductor

Qi Wang

Qi Wang

VP and Chief of Staff to the CEO at Cadence Design Systems, Inc.

Most of today’s most exciting new electronic products are not single-function, standalone devices, but rather are multi-function system devices, composed of subsystems, and connected into even larger systems. Being at the core of any electronic system, the semiconductor technology is going through a sea change where tackling the traditional semiconductor issues such as timing, power, and performance becomes insufficient. Additional challenges include time-to-market, functional partitioning, communications protocols, IP selection, hardware-software verification, reliability, safety, and many others. In this presentation, the presenter will summarize the design challenges and highlight some solutions for system design enablement in this increasingly complex environment.

Dr. Qi Wang is the VP and Chief of Staff to the CEO at Cadence Design Systems, Inc. He has over 16 years experience in EDA and held various R&D and marketing positions at Cadence. Prior to his current role, he is the Product Marketing Group Director of the Solutions Marketing group, with a focus on Cadence low power and mixed signal solutions. He is the chief architect of Common Power Format, which was contributed to Si2 and became the industry first open power format in early 2007. He held various positions in international standard organization like Si2 and IEEE. He had more than 20 papers published in various international conferences and journals. He also holds 7 US patents and a recipient of Cadence Outstanding Patent Award in 2010. In 2011, he received the Distinguished Service Award from Si2. Dr. Wang received his Ph.D. degree in Computer Engineering from University of Arizona and his B.S. degree from Shanghai Jiao Tong University.

Joint-Keynote III: Jan. 28, 2016 (8:30-10:00am)

Chairman: David Z. Pan, University of Texas at Austin, USA

Majority-based Synthesis for Nanotechnologies

Giovanni De Micheli

Giovanni De Micheli

Professor, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland

We study the logic synthesis of emerging nanotechnologies whose elementary devices abstraction is a majority voter. We argue that synthesis tools, natively supporting the majority logic abstraction, are the technology enablers. This is because they allow designers to validate majority-based nanotechnologies on large-scale benchmarks. We describe models and data- structures for logic design with majority-based nanotechnologies and we show results of applying new synthesis algorithms and tools. We conclude that new logic synthesis methods are required to achieve a fair assessment on emerging nanotechnologies.

Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering and of the Integrated Systems Centre at EPF Lausanne, Switzerland. He is program leader of the Nano-Tera.ch program. Previously, he was Professor of Electrical Engineering at Stanford University.He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983).
Prof. De Micheli is a Fellow of ACM and IEEE and a member of the Academia Europaea. His research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies, networks on chips and 3D integration. He is also interested in heterogeneous platform design including electrical components and biosensors, as well as in data processing of biomedical information. He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of eight other books and of over 600 technical articles. His citation h-index is 85 according to Google Scholar. He is member of the Scientific Advisory Board of IMEC (Leuven, B), CfAED (Dresden, D) and STMicroelectronics.
Prof. De Micheli is the recipient of the 2012 IEEE/CAS Mac Van Valkenburg award for contributions to theory, practice and experimentation in design methods and tools and of the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems. He received also the Golden Jubilee Medal for outstanding contributions to the IEEE CAS Society in 2000, the D. Pederson Award for the best paper on the IEEE Transactions on CAD/ICAS in 1987, and several Best Paper Awards, including DAC (1983 and 1993), DATE (2005) and Nanoarch (2010 and 2012).
He has been serving IEEE in several capacities, namely: Division 1 Director (2008-9), co-founder and President Elect of the IEEE Council on EDA (2005-7), President of the IEEE CAS Society (2003), Editor in Chief of the IEEE Transactions on CAD/ICAS (1997-2001). He has been Chair of several conferences, including Memocode (2014) DATE (2010), pHealth (2006), VLSI SOC (2006), DAC (2000) and ICCD (1989).

A Scalable Communication-Aware Compilation Flow for Programmable Accelerators

Jason Cong

Jason Cong

Chancellor's Professor, UCLA Computer Science Department
Director, Center for Domain-Specific Computing

Programmable accelerators (PA) are receiving increased attention in domain-specific architecture designs to provide more general support for customization. In a PA-rich system, computational kernels are compiled into predefined PA templates and dynamically mapped to real PAs at runtime. This imposes a demanding challenge on the compiler side – that is, how to generate high-quality PA mapping code. Another important concern is the communication cost among PAs: if not handled properly at compile time, data transfers among tens or hundreds of accelerators in a PA-rich system will limit the overall performance gain. In this paper we present an efficient PA compilation flow, which is scalable for mapping large computation kernels into PA-rich architectures. Communication overhead is modeled and optimized in the proposed flow to reduce runtime data transfers among accelerators. Experimental results show that for 12 computation-intensive standard benchmarks, the proposed approach significantly improves compilation calability, mapping quality and overall communication cost compared to state-of-art PA compilation approaches. We also evaluate the proposed flow on a recently developed PA-rich platform [1]; the final performance gain is improved by 49.5% on average.

Jason Cong received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Currently, he is a Chancellor’s Professor at the UCLA Computer Science Department, the director of Center for Domain-Specific Computing (CDSC). He served as the department chair from 2005 to 2008. Dr. Cong’s research interests include electronic design automation, energy-efficient computing, customized computing for big-data applications, and highly scalable algorithms. He has over 400 publications in these areas, including 10 Best Paper Awards, two 10-Year Most Influential Paper Awards, and the 2011 ACM/IEEE A. Richard Newton Technical Impact Award in Electric Design Automation. He was elected to an IEEE Fellow in 2000 and ACM Fellow in 2008. He is the recipient of the 2010 IEEE Circuits and System Society Technical Achievement Award "For seminal contributions to electronic design automation, especially in FPGA synthesis, VLSI interconnect optimization, and physical design automation."
Dr. Cong has graduated 33 PhD students. Nine of them are now faculty members in major research universities, including Cornell, Fudan Univ., Georgia Tech., Peking Univ., Purdue, SUNY Binghamton, UCLA, UIUC, and UT Austin. One of them is now an IEEE Fellow, six of them got the highly competitive NSF Career Award, and one of them received the ACM SIGDA Outstanding Dissertation Award. Dr. Cong has successfully co-founded three companies with his students, including Aplus Design Technologies for FPGA physical synthesis and architecture evaluation (acquired by Magma in 2003, now part of Synopsys), AutoESL Design Technologies for high-level synthesis (acquired by Xilinx in 2011), and Neptune Design Automation for ultra-fast FPGA physical design (acquired by Xilinx in 2013). Currently, he is a co-founder and the chief scientific advisor of Falcon Computing Solutions, a startup dedicated to enabling FPGA-based customized computing in data centers. Dr. Cong is also a distinguished visiting professor at Peking University.

Software and System Co-optimization in the era of Heterogeneous Computing

Michael Gschwind

Michael Gschwind

STSM & Senior Manager, System Architecture, IBM STG & IBM TJ Watson Research Center, USA

Escalating costs of semiconductor technology and its lagging performance relative to historic trends is motivating acceleration and specialization as more impactful means to increase system value. Targeted specialization is being increasingly pursued as an important way to achieve dramatic improvements in workload acceleration. This requires a broad understanding of workloads, system structures, and algorithms to determine what to accelerate / specialize, and how, i.e., via SW?; via HW?; or via SW+HW? which presents many choices, necessitating co-optimization of SW and HW. In this talk, we will focus on an application driven approach to software and system co-optimization, based on inventing new software algorithms, that have strong affinity to hardware acceleration. A High Level design methodology that is needed to enable targeted specialization in hardware will also be described.

Michael Gschwind is a Senior Technical Staff Member and Senior Manager in IBM’s Systems Group where he leads the definition of the IBM’s Power and mainframe architecture. In addition to his responsibilities for the enterprise server hardware architecture, he has also been chief architect for the new OpenPOWER little-endian Power software ecosystem for which he led the definition of the system and programming environment. Most recently, he served as chief architect for the innovations in the Power8, Power7 and z13 enterprise servers, and is currently chief architect for IBM’s next generation of servers. During his career at IBM, Mike has served as leader for many of IBM's microprocessor products, including Chief Architect roles for the Cell Broadband Engine and Blue Gene/Q. For the Cell architecture, Dr. Gschwind pioneered the concept of generally purpose programmable accelerators and their use for application acceleration based on high-level language programming. In addition to his leadership in the system design, Dr. Gschwind also developed the first Cell compiler and served as lead for the definition of the Cell software environment. Dr. Gschwind has published numerous articles and received over 150 patents in the area of computer architecture, hardware design, systems design, programming languages, and compiler technology. He has delivered numerous keynotes and invited talks at major conferences on architecture, systems and programming languages. In 2006, Dr. Gschwind was recognized as an IT Innovator and Influencer by InformationWeek. Dr. Gschwind is a member of the ACM SIGMICRO Executive Board, an ACM Distinguished Speaker, a Member of the IBM Academy of Technology, an IBM Master Inventor and an IEEE Fellow.


Last Updated on: Jan 7, 2016