Date: 22 Sept 2016 (Thur)
Venue: Lecture Hall, G013, N21, University of Macau
The Lecture is:
“Direct Sampling Receivers and Multi-GS/s High-Resolution ADCs”
The speaker is:
Prof. WU Jiangfeng
Professor, Tongji University, Shanghai, China
Jiangfeng Wu received B.E. degree in electronic engineering from Tsinghua University, China, in 1995, M.S. degree in electrical engineering from University of Pittsburgh in 2000, and Ph.D. degree in electrical and computer engineering from Carnegie Mellon University in 2002. From 2003 to 2015, he was with Broadcom Corporation in Irvine, CA, working on analog, RF and mixed-signal circuits for communications. From 2013 to 2015, he was an Associate Technical Director at Broadcom. Since 2009, he has been working on ultra-high-speed high-resolution analog-to-digital converters (ADCs) and their applications in communications. He was one of the architects and key contributors of Broadcom’s Full-Band Capture (FBC) technology which directly digitizes the entire GHz-wide spectrum using multi-GS/s ADCs. He led the development of Broadcom’s first high-speed high-resolution ADCs in both 28nm and 16nm nodes. He served in Broadcom’s analog process technology committee and central engineering patent review committee. In 2015, he joined Tongji University in Shanghai, China, and is now a professor in the College of Electronics and Information Engineering. He has published 22 technical papers. His paper on low-noise MEMS capacitive accelerometer published in 2004 has been cited 252 times (Google). Since 2011, he has published 10 papers in the area of high-speed data converters and wide-band transceivers. He has 13 granted US patents with 3 pending. He received Broadcom CEO Achievement Award in 2012, Analog Devices Outstanding Student Designer Award in 2002, and China National College Student Electronic Design Competition First Award in 1994.
In this talk, first a direct sampling full-band capture (FBC) receiver for cable and digital TV applications will be presented. It consists of a 0.18 um BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS direct RF sampling receiver based on a 2.7 GS/s analog-to-digital converter (ADC) embedded in a system-on-chip (SoC). The receiver is capable of receiving 158 256-QAM channels from 48 MHz to 1000 MHz simultaneously, achieving up to 10 Gb/s data throughput for data and video, while consuming 2.7 mW per 6-MHz channel.
Next this talk will present a single-channel 13b 4GS/s pipelined ADC using a multi-step capacitor and amplifier sharing frontend MDAC architecture assisted by a concurrent digital equalizer to reduce noise, distortion and power while overcoming common issues of SHA-less ADCs. It occupies 0.24mm2 area in 16nm CMOS and consumes 280mW power. It achieves 75dB peak SFDR, 68dB SFDR at Nyquist, -66dBFS noise level and 56dB SNDR at Nyquist. It has a Walden FoM of 135.8fJ/conv-step and a Schreier FoM of 154.5dB.
The workshop is open to the public. For more details, please refer to the poster.
For enquiry: State Key Laboratory of Analog and Mixed-Signal VLSI
Tel. No: (853) 8822-8796 / (853) 8822-8035 / (853) 8822-4430