State Key Laboratory of Analog and Mixed-Signal VLSI: AMSV Distinguished Lecture by Prof. Robert Bogdan Staszewski

The University Lecture on “All-Digital Phase-Locked Loops (ADPLL)” will take place as follows:

Date: 27 Jul 2017 (Thur)

Time: 09:00 - 13:00

Venue: Lecture Hall, G013, N21, University of Macau


The speaker is:

Prof. Robert Bogdan Staszewski
Full Professor, IEEE Fellow, University College Dublin


The Lecture is:

“All-Digital Phase-Locked Loops (ADPLL)”



The past several years has seen proliferation of all-digital phase-locked loops (ADPLL) for RF and high-performance frequency synthesis due to their clear benefits of flexibility, reconfigurability, transfer function precision, settling speed, frequency modulation capability, and amenability to integration with digital baseband and application processors. When implemented in nanoscale CMOS, the ADPLL also exhibits advantages of better performance, lower power consumption, lower area and cost over the traditional analog-intensive charge-pump PLL. In a typical ADPLL, a traditional VCO got directly replaced by a digitally controlled oscillator (DCO) for generating an output variable clock, a traditional phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for detecting phase departures of the variable clock versus the frequency reference (FREF) clock, and an analog loop RC filter got replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits are readily estimated and compensated using ”free” but powerful digital logic.

This lecture mainly contains three parts:

  1.  A system level view of the ADPLL including (1) Principles of phase-domain frequency synthesis (2) ADPLL closed-loop behavior (3) Direct frequency modulation of ADPLL (4) Alternative TX architectures using ADPLL and PA regulator (5) Survey of published ADPLL architectures; TDC-less ADPLL; cell-based ADPLL design.
  2.  A digitally controlled oscillator (DCO) lies at the heart of an all-digital phase-locked loop (ADPLL). It is based on an LC-tank with a negative resistance to perpetuate the oscillation— just like the traditional VCO, but with a significant difference in one of the components: instead of continuously tuned varactor (variable capacitor), the DCO now uses a large number of binary-controlled varactors. Each varactor can be placed in either high or low capacitative state. The composite varactor performs digital-to-capacitance conversion. This lecture presents a circuit and system level views of DCO.

A time-to-digital converter (TDC) is used in the ADPLL to perform the phase detection. It generates a digital variable phase or timestamps of the FREF edges in the units of the DCO clock period. The variable phase is a fixed-point digital word in which the fractional part is measured with a resolution of an inverter delay (about 10 ps in 40-nm CMOS). This lecture presents a system level view of TDC as well as its circuit-level implementation issues.



R. Bogdan Staszewski received BSEE (summa cum laude), MSEE and PhD from University of Texas at Dallas, USA, in 1991, 1992 and 2002, respectively.  From 1991 to 1995 he was with Alcatel in Richardson, Texas. He joined Texas Instruments in Dallas, Texas in 1995. In 1999 he co-started a Digital RF Processor (DRP) group in TI with a mission to invent new digitally intensive approaches to traditional RF functions. Dr. Staszewski served as a CTO of the DRP group between 2007 and 2009. In July 2009 he joined Delft University of Technology in the Netherlands where he is currently a part-time Full Professor. Since Sept. 2014 he is a Full Professor at University College Dublin (UCD) in Ireland. He has co-authored two books, four book chapters, 220 journal and conference publications, and holds 160 issued US patents. His research interests include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers. He is an IEEE Fellow and a recipient of IEEE Circuits and Systems Industrial Pioneer Award (


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