Biao Wang(Homepage)

Biao Wang

王彪

Steven

DCSP Research Line - PhD


Conference Papers and PresentationsTotal: 3
  1. 3. Biao Wang, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, "A 550μW 20kHz BW 100.8dB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65nm CMOS", Proc. IEEE Symposium on VLSI Circuits - VLSI 2018, , Jun-2018.
  2. 2. Biao Wang, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, "A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS", 2018 IEEE Symposium on VLSI Circuits, [Travel Grant Award] [Invited Special Issue in JSSC], Jun-2018.
  3. 1. Biao Wang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A high resolution multi-bit incremental converter insensitive to DAC mismatch error", Ph.D Research in Micro-electronics & Electronics (PRIME), , Jun-2016.



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