Mingqiang Guo(Homepage)

Mingqiang Guo

郭銘強

Frank

DCSP Research Line - Post-Doctoral Fellow


Journals and MagazinesTotal: 2
  1. 2. Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, "A 1.6GS/s 12.2mW 7/8-way Split Time-Interleaved SAR ADC achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration", IEEE Journal of Solid-State Circuits, Mar-2020.
  2. 1. Jiali Ma, Mingqiang Guo, Sai Weng Sin, R. P. Martins, "A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current", IEEE Transactions on Circuits and Systems II: Express Briefs, Oct-2018.
Conference Papers and PresentationsTotal: 4
  1. 4. Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, "A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing", IEEE Symposium on VLSI Circuits (VLSI), , Jun-2019.
  2. 3. Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, "A 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration", IEEE Custom Integrated Circuits Conference (CICC), , Apr-2019.
  3. 2. Jiaji Mao, Mingqiang Guo, Sai Weng Sin, R. P. Martins, "A 14-bit Split Pipeline ADC with Self-Adjusted Opamp-Sharing Duty Cycle", IEEE International Solid-State Circuits Conference – ISSCC 2018, Ph.D. Student Research Preview - Session 3, Paper No.7, Feb-2018.
  4. 1. Mingqiang Guo, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Split-based time-interleaved ADC with digital background timing-skew calibration", 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), , Jun-2017.



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