Wei Wang(Homepage)

Wei Wang

王瑋

Raistlin

DCSP Research Line - PhD


Journals and MagazinesTotal: 2
  1. 2. Wei Wang, Chi Hang Chan, Yan Zhu, R. P. Martins, "A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization", IEEE Journal of Solid-State Circuits, Jun-2020.
  2. 1. Bing Li, Ji-Ping Na, Wei Wang, Jia Liu, Qian Yang, Pui In Mak, "A 13-bit 8-kS/s ΔΣ Readout IC Using the ZCB Integrators with an Embedded Resistive Sensor Achieving 1.05-pJ/conversion-step and 65-dB PSRR", IEEE Transactions on VLSI systems, Apr-2019.
Conference Papers and PresentationsTotal: 1
  1. 1. Wei Wang, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A 5.35 mW 10 MHz Bandwidth CT Third-Order ∆∑ Modulator with Single Opamp Achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS", IEEE Asian Solid-State Circuits Conference (A-SSCC), (highlighted paper and suggested to JSSC special issue), pp.285-288, Nov-2017.



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