JIANG Yang(Homepage)

JIANG Yang

江洋

Tim

Email:yang.jiang

Wireless IC Research Line - Research Assistant Professor

IEEE Member

Academic Qualifications

  • Ph.D. in Electrical and Computer Engineering, University of Macau (2019)
  • M.Sc. in Electrical and Electronics Engineering, University of Macau (2012)
  • B.Sc. in Electrical and Electronics Engineering, University of Macau (2009)

Professional Experience

  • Research Assistant Professor, State Key Laboratory of Analog and Mixed Signal VLSI, University of Macau (Sep. 2019 – Present)
  • Postdoctoral Fellow, State Key Laboratory of Analog and Mixed Signal VLSI, University of Macau (Apr. 2019 – Sep. 2019)
  • Research Assistant, State Key Laboratory of Analog and Mixed Signal VLSI, University of Macau (Jan. 2019 – Apr. 2019)
  • Teaching Assistant, Faculty of Science and Technology, University of Macau, (Sep. 2012 - Jun. 2014)

Awards & Honors

  • Synopsys Academic Prize (for outstanding academic achievement), University of Macau, 2019
  • SSCS Predoctoral Achievement Award, IEEE Solid-State Circuits Society, 2018-2019
  • Postgraduate Studentship, University of Macau, 2012/2013, 2013/2014, 2014/2015
  • Third Prize in "Challenge Cup - National Undergraduate Curricular Academic Science and Technology Works Contest", China Association for Science and Technology, 2009
  • Ocean-Tech Award (for outstanding academic achievement), University of Macau, 2009
  • Dean's Honour List, University of Macau, 2008/2009

Research Interests

  • CMOS integrated DC-DC converters
  • On-chip power management circuits
  • High voltage drivers
  • Analog and mixed-signal IC design
 

Professional Services

  • Peer Reviewer for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Microelectronics Journal, IEICE Electronics Express, ISCAS, BioCAS...

 


Conference Papers and PresentationsTotal: 3
  1. 3. JIANG Yang, Man-Kay Law, Pui In Mak, R. P. Martins, "A 0.22-to-2.4V-Input Fine-Grained Fully-Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI) Topology Archiving 84.1% Peak Efficiency at 13.2μW/mm2", IEEE Int. Solid-State Circuit Conference (ISSCC), Digest of Technical Papers, accepted and [Invited Special Issue in JSSC], Jan-2018.
  2. 2. Biao Chen, JIANG Yang, Kwan-Ting Ng, Man-Kay Law, Pui In Mak, R. P. Martins, "A Wide Range High Efficiency Fully Integrated Switched-Capacitor DC-DC Converter with Fixed Output Spectrum Modulation", IEEE Int. Conference of Electron Devices and Solid-State Circuits (EDSSC), , Oct-2017.
  3. 1. JIANG Yang, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Clock-Jitter Sensitivity Reduction in CT Sigma-Delta Modulators Using Voltage-Crossing Detection DAC", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.



Back