JIANG Yang(Homepage)

JIANG Yang

江洋

Tim

Email:yang.jiang

Wireless IC Research Line - Research Assistant Professor

IEEE Member

Academic Qualifications

  • Ph.D. in Electrical and Computer Engineering, University of Macau (2019)
  • M.Sc. in Electrical and Electronics Engineering, University of Macau (2012)
  • B.Sc. in Electrical and Electronics Engineering, University of Macau (2009)

Professional Experience

University of Macau

  • Research Assistant Professor, State Key Laboratory of Analog and Mixed Signal VLSI, University of Macau (Sep. 2019 – Present)
  • Postdoctoral Fellow, State Key Laboratory of Analog and Mixed Signal VLSI, University of Macau (Apr. 2019 – Sep. 2019)
  • Research Assistant, State Key Laboratory of Analog and Mixed Signal VLSI, University of Macau (Jan. 2019 – Apr. 2019)
  • Teaching Assistant, Faculty of Science and Technology, University of Macau, (Sep. 2012 - Jun. 2014)

The University of Tokyo

  • Visiting Associate Research Fellow, Institute of Industrial Science (Jan. 2020 – Present)   

Awards & Honors

  • Synopsys Academic Prize (for outstanding academic achievement), University of Macau, 2019
  • SSCS Predoctoral Achievement Award, IEEE Solid-State Circuits Society, 2018-2019
  • Postgraduate Studentship, University of Macau, 2012/2013, 2013/2014, 2014/2015
  • Third Prize in "Challenge Cup - National Undergraduate Curricular Academic Science and Technology Works Contest", China Association for Science and Technology, 2009
  • Ocean-Tech Award (for outstanding academic achievement), University of Macau, 2009
  • Dean's Honour List, University of Macau, 2008/2009
  • "First Prize in IEEE Macau Student Project Competition", UM Student Branch of the IEEE, 2009.

Research Interests

  • CMOS integrated DC-DC converters
  • On-chip power management circuits
  • High voltage drivers
  • Analog and mixed-signal IC design
 

Professional Services

       Peer Reviewer :

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 
  • Microelectronics Journal 
  • IEICE Electronics Express 
  • IEEE International Symposium on Circuits and Systems (ISCAS) 2019, 2020 
  • IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2019 
  • IEEE Biomedical Circuits and Systems Conference (BioCAS) 2018 
  • IEEE Asia Symposium on Quality Electronic Design (ASQED) 2012

 


Journals and MagazinesTotal: 4
  1. 4. JIANG Yang, Man-Kay Law, Zhiyuan Chen, Pui In Mak, R. P. Martins, "Algebraic Series-Parallel-Based Switched-Capacitor DC-DC Boost Converter with Wide Input Voltage Range and Enhanced Power Density", IEEE Journal of Solid-State Circuits (JSSC), 2019, Vol. 54, Issue 11, Nov-2019.
  2. 3. Jiangchao Wu, Ka-Chon Lei, Hou-Man Leong, JIANG Yang, Man-Kay Law, Pui In Mak, R. P. Martins, "Fully Integrated High Voltage Pulse Driver Using Switched-Capacitor Voltage Multiplier and Synchronous Charge Compensation in 65-nm CMOS", IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), Vol. 66, Issue 10, Oct-2019.
  3. 2. JIANG Yang, Man-Kay Law, Pui In Mak, R. P. Martins, "Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck-Boost Switched-Capacitor DC-DC Converters", IEEE Journal of Solid-State Circuits (JSSC), Vol. 53, Issue 12, Dec-2018.
  4. 1. Chenyan Cai, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Excess-Loop-Delay Compensation Technique for CT Delta Sigma Modulator with Hybrid Active-Passive Loop-Filters", Analog Integrated Circuits and Signal Processing, Vol. 76, Issue 1, May-2013.
Conference Papers and PresentationsTotal: 16
  1. 16. Jiangchao Wu, Ka-Chon Lei, Hou-Man Leong, JIANG Yang, Man-Kay Law, Pui In Mak, R. P. Martins, "Fully Integrated High Voltage Pulse Driver Using Switched-Capacitor Voltage Multiplier and Synchronous Charge Compensation in 65-nm CMOS", in IEEE Int'l Symposium on IC and Systems (ISICAS), pp. 1768 - 1772, Venice, Italy, Aug-2019.
  2. 15. Zhiyuan Chen, JIANG Yang, Man-Kay Law, Pui In Mak, Xiaoyang Zeng, R. P. Martins, "Piezoelectric Energy Harvesting Interface using Split-Phase Flipping-Capacitor Rectifier (SPFCR) and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy Extraction Improvement", in IEEE International Solid-State Circuits Conference (ISSCC), Dig. Tech. Papers, Feb-2019.
  3. 14. JIANG Yang, Man-Kay Law, Pui In Mak, R. P. Martins, "A 0.22-to-2.4V-Input Fine-Grained Fully-Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI) Topology Archiving 84.1% Peak Efficiency at 13.2μW/mm2", IEEE Int. Solid-State Circuit Conference (ISSCC), Digest of Technical Papers, accepted and [Invited Special Issue in JSSC], pp. 422-423, Feb-2018.
  4. 13. Biao Chen, JIANG Yang, Kwan-Ting Ng, Man-Kay Law, Pui In Mak, R. P. Martins, "A Wide Range High Efficiency Fully Integrated Switched-Capacitor DC-DC Converter with Fixed Output Spectrum Modulation", IEEE Int. Conference of Electron Devices and Solid-State Circuits (EDSSC), , Oct-2017.
  5. 12. JIANG Yang, Man-Kay Law, Pui In Mak, R. P. Martins, "A 0.22-to-2.4V Input Fully Integrated Buck-Boost SC DC-DC Converter with Cell-Spliced Power Stage and Domain-Adaptive Switch Drivers", IEEE International Solid-State Circuits Conference, - Student Research Preview (ISSCC-SRP), San Francisco, USA, Feb-2017.
  6. 11. Yun Du, Tao He, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Continuous-Time VCO-Assisted VCO-Based ΣΔ Modulator with 76.6dB SNDR and 10MHz BW", in IEEE International Symposium on Circuits and Systems (ISCAS), , May-2013.
  7. 10. Yun Du, Tao He, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A robust NTF Zero Optimization Technique for both Low and High OSRs Sigma-Delta Modulators", in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), , Dec-2012.
  8. 9. Tao He, Yun Du, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A DT 0–2 MASH ΣΔ Modulator with VCO-Based Quantizer for Enhanced Linearity", in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), , Dec-2012.
  9. 8. Zhijie Chen, JIANG Yang, Chenyan Cai, He-Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application", in IEEE Asian Solid State Circuits Conference (A-SSCC), , Nov-2012.
  10. 7. Chenyan Cai, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators", in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), , Aug-2012.
  11. 6. Tao He, JIANG Yang, Yun Du, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 10MHz BW 78dB DR CT ΣΔ Modulator with Novel Switched High Linearity VCO-Based Quantizer", in IEEE International Symposium on Circuits and Systems (ISCAS), , May-2012.
  12. 5. JIANG Yang, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Clock-Jitter Sensitivity Reduction in CT Sigma-Delta Modulators Using Voltage-Crossing Detection DAC", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
  13. 4. Tao He, Yun Du, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Dual-VCO-Based Quantizer with Highly Improved Linearity and Enlarged Dynamic Range", in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), , Aug-2011.
  14. 3. Chenyan Cai, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time ΣΔ Modulators", in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), , Aug-2011.
  15. 2. JIANG Yang, Kim Fai Wong, Chenyan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in Continuous-Time Sigma-Delta Modulators", in IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp.547-550, Dec-2010.
  16. 1. JIANG Yang, Kim-Fai Wong, Chenyan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators", in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), , Dec-2010.



Back