Sai Weng Sin(Homepage)

Sai Weng Sin

冼世榮

Terry

Email:terryssw

Phone:(+853)8822-8795

Room Number:N21-3007c

Teaching Coordinator


Patents and Technology TransferTotal: 1
  1. 1. Biao Wang, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, "Single-Loop Linear-Exponential Multi-Bit Incremental Analog-to-Digital Converter", US Patent, No. 10,644,718 B1, , 05/05/2020
Journals and MagazinesTotal: 7
  1. 7. Wen-Liang Zheng, Yuan Ren, Chi-Seng Lam, Sai Weng Sin, Weng-Keong Che, Ran Ding, R. P. Martins, "A 470nA quiescent current and 92.7%/94.7% efficiency DCT/PWM control buck converter with seamless mode transition for IoT application", IEEE Transactions on Circuits and Systems I - Regular Papers (TCAS-I), Jul-2020.
  2. 6. Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, "A 1.6GS/s 12.2mW 7/8-way Split Time-Interleaved SAR ADC achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration", IEEE Journal of Solid-State Circuits, Mar-2020.
  3. 5. Liang Qi, Ankesh Jain, Jiang DongYang, Sai Weng Sin, R. P. Martins, Maurits Ortmanns, "A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance", IEEE Journal of Solid-State Circuits, Mar-2020.
  4. 4. Wen-Ming Zheng, Wen-Liang Zheng, Chi-Wa U, Chi-Seng Lam, Yan Lu, Sai Weng Sin, Man-Chung Wong, R. P. Martins, "Analysis, Design and Control of an Integrated Three-Level Buck Converter under DCM Operation", Journal of Circuits, Systems and Computers, Mar-2020.
  5. 3. Wen-Ming Zheng, Wen-Liang Zheng, Chi-Wa U, Chi-Seng Lam, Yan Lu, Sai Weng Sin, Man-Chung Wong, R. P. Martins, "Analysis, design and control of an integrated three-level buck converter under DCM operation", Journal of Circuits, Systems, and Computers, Jan-2020.
  6. 2. U-Fat Chio, Kuo-Chih Wen, Sai Weng Sin, Chi-Seng Lam, Yan Lu, Franco Maloberti, R. P. Martins, "An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery", IEEE Journal of Solid-State Circuits, Oct-2019.
  7. 1. Biao Wang, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, "A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS", IEEE Journal of Solid-State Circuits, Apr-2019.
Conference Papers and PresentationsTotal: 6
  1. 6. Jiang DongYang, Liang Qi, Sai Weng Sin, Franco Maloberti, R. P. Martins, "A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS", 2020 Symposium on VLSI Circuits Digest of Technical Papers, , Jun-2020.
  2. 5. Jiang DongYang, Liang Qi, Sai Weng Sin, Franco Maloberti, R. P. Martins, "A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-order ÄÓ Modulator with Digital Feedforward Extrapolation in 28nm CMOS", CICC 2020, , Mar-2020.
  3. 4. Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, "A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing", IEEE Symposium on VLSI Circuits (VLSI), , Jun-2019.
  4. 3. Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, "A 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration", IEEE Custom Integrated Circuits Conference (CICC), , Apr-2019.
  5. 2. Liang Qi, Ankesh Jain, Jiang DongYang, Sai Weng Sin, R. P. Martins, Maurits Ortmanns, "A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS", IEEE International Solid-State Circuits Conference (ISSCC 2019), pp.336-338, Feb-2019.
  6. 1. Jianyang Deng, Chi-Seng Lam, Man-Chung Wong, Lei Wang, Sai Weng Sin, R. P. Martins, "A Power Quality Indexes Measurement System Platform with Remote Alarm Notification", 44th Annual Conference of the IEEE Industrial Electronics Society (IECON 2018), , Oct-2018.



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