Contact Hour: Tue 10:00-11:00, Fri 10:00-11:00
For his research works, please visit: https://sites.google.com/site/ychenscholar/Home
Yong Chen received the B.Eng. degree in electronic and information engineering, Communication University of China (CUC), Beijing, China, in 2005, and the Ph.D. in Engineering degree in microelectronics and solid-state electronics, Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing, China, in 2010.
From 2010 to 2013, He worked as Post-Doctoral Researcher in Institute of Microelectronics, Tsinghua University, Beijing, China. From 2013 to 2016, he was Research Fellow responsible for high-speed (40+Gb/s) wireline communication and Low Energy Electronic Systems (LEES) project under the Singapore-MIT Alliance for Research and Technology (SMART) on RF CMOS transceiver in VIRTUS/EEE, Nanyang Technological University, Singapore. He is now an Assistant Professor of the State Key Laboratory of Analog and Mixed-Signal VLSI (AMSV) of University of Macau, Macao, China, since March 2016.
His research interests include analog/biomedical detection and RF integrated circuit, mm-wave system and circuit, high-speed on-chip and chip-to-chip Electrical/Optical Interconnects
- Ph.D. in Microelectronics and Solid-State Electronics, Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), China (2010)
- B.S. in Electronic and Information Engineering, Communication University of China, China (2005)
Institute of Microelectronics
- Assistant Professor, Institute of Microelectronics (IME), University of Macau (Apr. 2019 – Present)
State-Key Laboratory of Analog and Mixed-Signal VLSI
- Assistant Professor, State-Key Lab. of Analog and Mixed-Signal VLSI (AMSV), University of Macau (Mar. 2016 – Present)
- Research Fellow in Nanyang Technological University, Singapore (Oct. 2013 – Feb. 2016)
- Post-doctoral in Institute of Microelectronics, Tsinghua University, Beijing, China (Jul. 2010 – Sep. 2013)
7. Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, "A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS", IEEE Asia Pacific Conference on Circuits and Systems, , Nov-2019.
5. Hao Guo, Yong Chen, Pui In Mak, R. P. Martins, "A 0.08mm2 25.5-to-29.9GHz Multi-Resonant-RLCM-Tank VCO Using a Single-Turn Multi-Tap Inductor and CM-Only Capacitors Achieving 191.6-dBc/Hz FOM and 130kHz 1/f3 PN Corner", IEEE International Solid-State Circuits Conference (ISSCC), pp. 410-412, Feb-2019.
3. Yong Chen, Pui In Mak, Yumei Zhou, Hao Ju, Li Zhang, He Qian, Yan Wang, Zhiping Yu, "A 6-bit 1.3-GS/s Flash ADC using a Gain-Compensated THA and an Offset-Averaging Preamplifier Array", in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, May-2011.
2. Yong Chen, Pui In Mak, Yumei Zhou, Hao Ju, Li Zhang, He Qian, Yan Wang, Zhiping Yu, "A Fast Lock-in PLL Using a Quadratic V-I Self-Tracking Charge Pump and a Replica-Biased Ring VCO", IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1872-1875, May-2011.