Yong Chen(Homepage)

Yong Chen

陳勇

Nick

Email:ychen

Phone:(+853) 8822-4470

Room Number:N21-3015g

Assistant Professor

Contact Hour: Tue 10:00-11:00, Fri 10:00-11:00

For his research works, please visit: https://sites.google.com/site/ychenscholar/Home

 

Biography

    Yong Chen received the B.Eng. degree in electronic and information engineering, Communication University of China (CUC), Beijing, China, in 2005, and the Ph.D. in Engineering degree in microelectronics and solid-state electronics, Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing, China, in 2010.

    From 2010 to 2013, He worked as Post-Doctoral Researcher in Institute of Microelectronics, Tsinghua University, Beijing, China. From 2013 to 2016, he was Research Fellow responsible for high-speed (40+Gb/s) wireline communication and Low Energy Electronic Systems (LEES) project under the Singapore-MIT Alliance for Research and Technology (SMART) on RF CMOS transceiver in VIRTUS/EEE, Nanyang Technological University, Singapore. He is now an Assistant Professor of the State Key Laboratory of Analog and Mixed-Signal VLSI (AMSV) of University of Macau, Macao, China, since March 2016.

    His research interests include analog/biomedical detection and RF integrated circuit, mm-wave system and circuit, high-speed on-chip and chip-to-chip Electrical/Optical Interconnects

Academic Qualifications

  • Ph.D. in Microelectronics and Solid-State Electronics, Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), China (2010)
  • B.S. in Electronic and Information Engineering, Communication University of China, China (2005)

Professional Experience

Institute of Microelectronics

  • Assistant Professor, Institute of Microelectronics (IME), University of Macau (Apr. 2019 – Present)

State-Key Laboratory of Analog and Mixed-Signal VLSI

  • Assistant Professor, State-Key Lab. of Analog and Mixed-Signal VLSI (AMSV), University of Macau (Mar. 2016 – Present)

Others

  • Research Fellow in Nanyang Technological University, Singapore (Oct. 2013 – Feb. 2016)
  • Post-doctoral in Institute of Microelectronics, Tsinghua University, Beijing, China (Jul. 2010 – Sep. 2013)

Research

Research Interests

  • Analog/mixed-signal CMOS integrated circuits
  • RF and mm-wave communication systems and circuits
  • High-speed on-chip and chip-to-chip electrical & optical interconnects

 

 

Theses Supervision

  • 10         PhD Theses (4 in NTU)
  • 4           Master Theses (1 in Tsinghua University and 1 in NTU)
  • 7           Undergraduate Final-Year Theses (3 in Tsinghua University)

 

PhD Thesis

Period

Research Topic

Zunsong Yang

2017-Present

Fully Integrated Multi-Mode Tens-of-Gb/s Transmitter

Xiaoteng Zhao

2017-Present

Tens-of-Gb/s Multi-Mode CDR

Hao Guo

2017-Present

Tens-of-Gb/s Bidirectional Transceiver

Yunbo Huang

2018-Present

High-Speed Wireline Circuits in Nanoscale CMOS

Lin Wang

2019-Present

High-Speed Wireline Circuits in Nanoscale CMOS

Xinxin Shi

2019-Present

High-Speed Wireline Circuits in Nanoscale CMOS

 

Master Thesis

Period

Research Topic

Xinyi Ge

2016-2019

40Gb/s Return-Zero-Based BBCDR

Jiafei Yu

2018-Present

Calibration-Free Multi-Phase Dual-Loop Phase Rotator

 

BSc Thesis

Period

Research Topic

Jawei Xu

2016-2017

A 20Gb/s Adaptive Equalizer Employing Slope-Detection Technique

Son Pang Chan

2016-2017

A 20Gb/s Adaptive Equalizer Employing Slope-Detection Technique

Sao Son Lam

2017-2018

Analysis and Design of 40Gb/s Automatic Gain Control Amplifier

Ian Chak Che

2017-2018

Analysis and Design of 40Gb/s Automatic Gain Control Amplifier

Research Funds

Role

Project Title

Funding Source

Year

PI

High-Frequency High-Performance PLL

Hisilicon, Huawei

2020-2021

PI

Research and Application of key techniques for automatic Test of Beidou Communication equipment

Guangzhou Science and Technology Innovation and Development of Special Funds

2019-2021

Co-PI

Adaptive PAM4/NRZ Receiver Front Ends with Dynamic Reference Voltage

Univ. of Macau MYRG

2019-2021

Co-PI

Tunable Bandwidth-Extension 28-nm CMOS Amplifiers for 60+ Gb/s Signaling

Univ. of Macau MYRG

2018-2020

PI

Low-Power Multi-Mode Transmitters with Simplified Hardware and Quadrature Clocking Scheme for 400-Gb/s Ethernet

Univ. of Macau MYRG

2018-2020

PI

Power-Efficient Wireline Equalization Techniques for 400Gb/s Ethernet

Univ. of Macau SRG

2017-2018

 

Professional Affiliations

 

Professional Services (External)

  • Editorial Board Member of Journal of Electrical and Electronic Engineering (JEEE)  (2018-2020)
  • Technical Program Committee Member of APCCAS’2019
  • Committee Member of APCCAS’2014
  • Reviewer of PLL textbook, B. Razavi
  • Reviewer of IEEE Journal of Solid-State Circuits (JSSC)
  • Reviewer of IEEE Solid-State Circuits Letters (SSC-L)
  • Reviewer of IEEE Trans. on Circuits and Systems I: Regular Papers (TCAS-I)
  • Reviewer of IEEE Trans. on Circuits and Systems II: Express Briefs (TCAS-II)
  • Reviewer of IEEE Trans. on Microwave Theory and Techniques (TMTT)
  • Reviewer of IEEE Trans. on Very Large Scale Integration (VLSI) Systems (TVLSI)
  • Reviewer of Microelectronics Journal
  • Reviewer of IET Electronics Letters (EL)
  • Reviewer of IEEE International Symposium on Circuits and Systems (ISCAS) 2013-2015

Professional Services (Internal)

  • Selection Committee Member, Assistant Professors for State-Key Laboratory of Analog and Mixed-Signal VLSI (Dec./2018)
  • Committee on Teaching and Learning Enhancement (2018-present)
  • College Affiliates of SHIU PONG COLLEGE (2018-present)
  • Defence Examination Committee of PhD Oral Defense on 6/May/2019
  • Academic (Working Secretary) of PhD Oral Defense on 18/Jan./2019
  • TAC Member of PhD QE on 2/July/2018
  • Defence Examination Committee of Master Oral Defense on 16/Jul./2018
  • Summer Research Programme for Undergraduate Students (Jun./2019 – Jul./2019)

 

Teaching Experience

B.Sc. Courses

  • Digital Signal Processing (ECEN3001)
  • Special Topic in ECE (ECEB451)
  • Engineering in Society (ECEB150)
  • Design Project I (ECEB410)
  • Design Project II (ECEB420)

M.Sc. Courses

  • Academic Thesis (ECEN7999)

Ph.D. Courses

  • Advance Topics in Electrical and Computer Engineering (ELCE818)
  • Research Writing (SCTE802)
  • Doctoral Thesis (ECEN8999)

Patents Issued

  1. Yong Chen et al., “A Biquad Cell for Implementation of Zero-Pole Type High-Order Filter,”Chinese Patent, Granted, No. ZL200810227119.7, Nov. 2010.
  2. Yong Chen et al., “A Gm-C Biquad Cell for Implementation of Zero- Pole Type High-Order Filter,” Chinese Patent, Granted, No. ZL200810226686.0, Jun. 2012.
  3. Yong Chen et al., “A Biquad Cell Based on Mixed Integrator for Implementation of Zero Pole Type High-Order Filter,” Chinese Patent, Granted, No. ZL200810227129.0, Jul. 2011.
  4. Yong Chen et al., “A Biquad Cell Based on Negative-Feedback Mixed Integrator,” Chinese Patent, Granted, No. ZL200810227128.6, Jan. 2012.
  5. Yong Chen et al., “A Reversed Nested Gm-C Compensation circuit,” Chinese Patent, Granted, No. ZL200810224721.5, Jan. 2012.
  6. Yong Chen et al., “A Biquad Cell with Enhanced Quality factor of Zero,” Chinese Patent, Granted, No. ZL200810227127.1, Feb. 2012.
  7. Yong Chen et al., “An Ultra Low Voltage Biquad Cell for Implementation of Bandpass Filter,”Chinese Patent, Granted, No. ZL200910303498.8, Oct. 2011.
  8. Yong Chen et al., “An Ultra Low Voltage NAND Gate,” Chinese Patent, Granted, No. ZL201110101066.6, Oct. 2012.
  9. Yong Chen et al., “A Fast Locking Charge Pump Phase Locked Loop,” Chinese Patent, Granted, No. ZL200910238759.2, Jan. 2013.
  10. Yong Chen et al., “A Self Tracking Switch-type Charge Pump for PLL,” Chinese Patent, Granted, No. ZL200910091962.1, Feb. 2013.
  11. Yong Chen et al., “A Self Tracking Current-type Charge Pump for PLL,” Chinese Patent, Granted, No. ZL200910238761.X, Feb. 2013.
  12. Yong Chen et al., “A Biquad Cell Based on Common-Drain Positive-Feedback,” Chinese Patent, Granted, No. ZL200910238766.2, May 2013.
  13. Yong Chen et al., “A Biquad Cell Based on Common-Source Positive-Feedback,” Chinese Patent, Granted, No. ZL200910238765.8, May 2013.   
  14. Yong Chen et al., “A Floating Differential Active Inductor Based on Positive-Feedback*,” Chinese Patent, Granted, No. ZL201110002682.6, Jul. 2013.
  15. Yong Chen et al., “A Floating Differential Active Inductor Based on Positive-Feedback*,” Chinese Patent, Granted, No. ZL201110046906.3, Jun. 2013.
  16. Yong Chen et al., “A Bandpass Filter Based on Negative-Feedback,” Chinese Patent, Granted, No. ZL201110101166.9, Jun. 2013.
  17. Yong Chen et al., “An Active Lowpass Filter Based on Inductor Substituted Method with Positive-Feedback*,” Chinese Patent, Granted, No. ZL201110095277.3, Dec. 2013.
  18. Yong Chen et al., “An Active Lowpass Filter Based on Inductor Substituted Method with Positive-Feedback*,” Chinese Patent, Granted, No. ZL201110095576.7, Oct. 2013.

[Note: (1) Above issued patents are first author patents; (2) Patents (14*, 15*) and (17*, 18*) are the same name, respectively, but they are based on different specific implementation methods. This naming method is allowed in Mainland China.]

 


Journals and MagazinesTotal: 16
  1. 16. Haohong Yu, Yong Chen, Chirn Chye Boon, Chenyang Li, Pui In Mak, R. P. Martins, "A 0.044-mm2 0.5-to-7-GHz resistor-plus-source-follower-feedback noise-cancelling LNA achieving a flat NF of 3.3±0.45 dB", IEEE Transactions on Circuits and Systems - II, Jan-2019.
  2. 15. Lingshan Kong, Yong Chen, Chirn Chye Boon, Pui In Mak, R. P. Martins, "A wideband inductorless dB-linear automatic-gain control amplifier using a single-branch negative exponential generator for wireline applications", IEEE Transactions on Circuits and Systems - I, Oct-2018.
  3. 14. Yong Chen, Pui In Mak, Chirn Chye Boon, R. P. Martins, "A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin", IEEE Transactions on Circuits and Systems - I, Sep-2018.
  4. 13. Hao Guo, Yong Chen, Pui In Mak, R. P. Martins, "A 0.083-mm2 25.2-to-29.5 GHz Multi-LC-Tank Class-F234 VCO with a 189.6-dBc/Hz FOM", IEEE Solid-State Circuits Letters, Apr-2018.
  5. 12. Yong Chen, Pui In Mak, Haohong Yu, Chirn Chye Boon, R. P. Martins, "An Area-Efficient and Tunable Bandwidth-Extension Technique for a Wideband CMOS Amplifier Handling 50+ Gb/s Signaling", IEEE Transactions on Microwave Theory and Techniques, Dec-2017.
  6. 11. Yong Chen, Pui In Mak, Chirn Chye Boon, R. P. Martins, "A 27-Gb/s Time-Interleaved Duobinary Transmitter Achieving 1.44-mW/Gb/s FOM in 65-nm CMOS", IEEE Microwave and Wireless Components Letters, Sep-2017.
  7. 10. Yong Chen, Pui In Mak, Yan Wang, "A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable Active Inductor for 10-Gb/s I/O Links", IEEE Transactions on Very Large Scale Integration Systems, May-2015.
  8. 9. Yong Chen, Pui In Mak, Li Zhang, Yan Wang, "A 0.002-mm2 6.4-mW 10-Gb/s Full-Rate Direct DFE Receiver with 59.6% Horizontal Eye Opening at 10-12 BER under 23.3-dB Channel Loss at Nyquist", IEEE Transactions on Microwave Theory and Techniques, Dec-2014.
  9. 8. Yong Chen, Pui In Mak, Stefano D'Amico, Li Zhang, He Qian, Yan Wang, "A Single-Branch Third-Order Pole–Zero Low-Pass Filter With 0.014-mm2 Die Size and 0.8-kHz (1.25-nW) to 0.94-GHz (3.99-mW) Bandwidth–Power Scalability", IEEE Transactions on Circuits and Systems – II, Nov-2013.
  10. 7. Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, "0.013 mm2, kHz-to-GHz-bandwidth, thirdorder all-pole lowpass filter with 0.52-to- 1.11 pW/pole/Hz efficiency", IET Electronics Letters, Oct-2013.
  11. 6. Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, "Pre-Emphasis Transmitter (0.007mm2, 8Gbit/s, 0-14dB) with Improved Data Zero-Crossing Accuracy in 65nm CMOS", IET Electronics Letters, Jul-2013.
  12. 5. Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, "A 0.0012mm2, 8mW, Single-to-Differential Converter with <1.1% Data Cross Error and <3.4ps RMS Jitter up to 14Gb/s Data Rate", IET Electronics Letters, May-2013.
  13. 4. Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, "A Fifth-Order 20-MHz Transistorized- -Ladder LPF With 58.2-dB SFDR, 68- Efficiency, and 0.13- Die Size in 90-nm CMOS", IEEE Transactions on Circuits and Systems – II, Jan-2013.
  14. 3. Yong Chen, Pui In Mak, L. Zhang, Y. Wang, "A 0.07mm2, 2mW, 75MHz-IF, 4th-Order BPF Using a Source-Follower-Based Resonator in 90nm CMOS", IET Electronics Letters, May-2012.
  15. 2. Yong Chen, Pui In Mak, Yumei Zhou, "Self-Tracking Charge Pump for Fast-Locking PLL", IET Electronics Letters, May-2010.
  16. 1. Yong Chen, Pui In Mak, Yumei Zhou, "Mixed-Integrator Biquad for Continuous-Time Filters", IET Electronics Letters, Apr-2010.
Conference Papers and PresentationsTotal: 6
  1. 6. Zunsong Yang, Yong Chen, Shiheng Yang, Pui In Mak, R. P. Martins, "A 25.4-to-29.5GHz 10.2mW Isolated-Sub-Sampling PLL (iSS-PLL) Achieving -252.9dB Jitter-power FOM and -63dBc Reference Spur", IEEE International Solid-State Circuits Conference (ISSCC), pp. 270-272, Feb-2019.
  2. 5. Hao Guo, Yong Chen, Pui In Mak, R. P. Martins, "A 0.08mm2 25.5-to-29.9GHz Multi-Resonant-RLCM-Tank VCO Using a Single-Turn Multi-Tap Inductor and CM-Only Capacitors Achieving 191.6-dBc/Hz FOM and 130kHz 1/f3 PN Corner", IEEE International Solid-State Circuits Conference (ISSCC), pp. 410-412, Feb-2019.
  3. 4. Yong Chen, Pui In Mak, Jiale Yang, Ruifeng Yue, Yan Wang, "Comparator with Built-in Reference Voltage Generation and Split-ROM Encoder for a High-Speed Flash ADC", International Symposium on Signals, Circuits and Systems (ISSCS), pp. 1-4, Jul-2015.
  4. 3. Yong Chen, Pui In Mak, Yumei Zhou, Hao Ju, Li Zhang, He Qian, Yan Wang, Zhiping Yu, "A 6-bit 1.3-GS/s Flash ADC using a Gain-Compensated THA and an Offset-Averaging Preamplifier Array", in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, May-2011.
  5. 2. Yong Chen, Pui In Mak, Yumei Zhou, Hao Ju, Li Zhang, He Qian, Yan Wang, Zhiping Yu, "A Fast Lock-in PLL Using a Quadratic V-I Self-Tracking Charge Pump and a Replica-Biased Ring VCO", IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1872-1875, May-2011.
  6. 1. Yong Chen, Pui In Mak, Yumei Zhou, "Source-follower-based bi-quad cell for continuous-time zero-pole type filters", of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3629-3632, May-2010.



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