Conference Papers and PresentationsTotal: 435
  • Pui In Mak, R. P. Martins, "A 0.46mm2 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65nm CMOS", ", IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp 172-174, Feb-2011.
  • He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS", IEEE International Solid-State Circuit Conference (ISSCC),, pp. 188-189, Feb-2011.
  • Chio-In Ieong, Mang I Vai, Peng Un Mak, Pui In Mak, "ECG Heart Beat Detection Via Mathematical Morphology and Quadratic Spline Wavelet Transform", IEEE International Conference on Consumer Electronics (ICCE), pp 609- 610, Jan-2011.
  • Yang Jiang, Kim Fai Wong, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators", IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1011-1014, Dec-2010.
  • Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, "An Efficient DAC and Interstage Gain Error Calibration Technique For Multi-Bit Pipelined ADCs", IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 208-211, Dec-2010.
  • Guohe Yin, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Zhihua Wang, "An Ultra Low Power 9-bit 1-MS/s Pipelined SAR ADC for Bio-medical Applications", IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 878-881, Dec-2010.
  • Yang Jiang, Kim Fai Wong, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in Continuous-Time Sigma-Delta Modulators", IEEE International Conference on Electronics, Circuits and Systems (ICECS, pp. 547-550, Dec-2010.
  • JIANG Yang, Kim Fai Wong, Chenyan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in Continuous-Time Sigma-Delta Modulators", in IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp.547-550, Dec-2010.
  • JIANG Yang, Kim-Fai Wong, Chenyan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators", in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), , Dec-2010.
  • He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Process-insensitive Current-Controlled Delay Generator with Threshold Voltage Compensation", IEEE Asian Solid-State Circuits Conference – ASSCC 2010, pp. 1-4, Nov-2010.